// +FHDR----------------------------------------------------------
// Copyright (c) 2023, RJMicro Technology Co.,Ltd.
// RJMicro Confidential Proprietary
// ---------------------------------------------------------------
// FILE NAME       : .v
// DEPARTMENT      : IC Dept
// AUTHOR          :
// AUTHOR'S EMAIL  :
// ---------------------------------------------------------------
//
// Description     :
// 12'h000  CTRLR0
// 12'h004  CTRLR1
// 12'h008  SSIENR
// 12'h00C  MWCR
// 12'h010  SER
// 12'h014  BAUDR
// 12'h018  TXFTLR
// 12'h01C  RXFTLR
// 12'h020  TXFLR
// 12'h024  RXFLR
// 12'h028  SR
// 12'h02C  IMR
// 12'h030  ISR
// 12'h034  RISR
// 12'h038  TXOICR
// 12'h03C  RXOICR
// 12'h040  RXUICR
// 12'h044  MSTICR
// 12'h048  ICR
// 12'h04C  DMACR
// 12'h050  DMATDLR
// 12'h054  DMARDLR
// 12'h058  IDR
// 12'h05C  SSI_VERSION_ID
// 12'h060  DR
// 12'h0F0  RX_SAMPLE_DLY
// 12'h0F8  TXD_DRIVE_EDGE
// -FHDR
// ---------------------------------------------------------------

module spi_regfile (
    output                 ctrlr0_srl          ,
    input                  pclk                ,
    input                  prstn               ,

    input                  psel                ,
    input  [11:0]          paddr               ,
    input                  penable             ,
    input                  pwrite              ,
    input  [31:0]          pwdata              ,
//    output                pready              ,
//    output                pslverr             ,
    output [31:0]          prdata
);

// ------------------------------------------------------------
// APB write read enable
// ------------------------------------------------------------
reg     [31:0]  ff_rdata;
wire            read_en   = psel && (~penable) && (~pwrite);
wire            write_en  = psel && (~penable) && pwrite;
wire    [11:0]  addr      = paddr;
wire    [31:0]  wdata     = pwdata;

always @(posedge pclk or negedge prst) begin
    if (!prst)
        prdata <= 32'b0;
    else if (read_en) 
        prdata <= ff_rdata[31:0];
end

// ------------------------------------------------------------
// Internal Signals
// ------------------------------------------------------------
reg             ff_ctrlr0_srl       ;


// ------------------------------------------------------------
// write_process
// ------------------------------------------------------------
wire     wren_ctrlr0         = write_en & (addr[11:2] == 10'h0);

always @(posedge pclk or negedge prstn) begin
    if (!prstn)
        ff_ctrlr0_srl <= 1'h0;
    else if (wren_ctrlr0) begin
        ff_ctrlr0_srl <= wdata[11];
    end
end


// ------------------------------------------------------------
// read_process
// ------------------------------------------------------------

wire  [31:0]  wir_r_ctrlr0   = {20'h0, ff_ctrlr0_srl, 11'h0};

always @ (*) begin
    ff_rdata = 32'h0;
    if (read_en) begin
        case (addr[11:2])
            10'b0000000000     :    ff_rdata = wir_r_ctrlr0;
            default: ff_rdata = 32'h0;
        endcase
    end
end
// ------------------------------------------------------------
// Assign
// ------------------------------------------------------------
assign  ctrlr0_srl          = ff_ctrlr0_srl       ;
// ------------------------------------------------------------
// End of the module
// ------------------------------------------------------------
endmodule
